PCIe 8.0 Specification Details 1 TB/s Speeds for Future GPUs

The PCI-SIG has outlined the first full draft of the PCIe 8.0 specification, setting a target of 256 GT/s raw bit rate that delivers up to 1 TB/s of bidirectional bandwidth in an x16 configuration. The organization released the draft version 0.5, which locks in key architectural elements including electrical, logical, compliance, and software aspects while leaving some parameters open for further refinement. This marks the initial milestone after the PCIe 7.0 specification was finalized last year.

Current high-end graphics cards such as the RTX 5090 operate on PCIe 5.0, which provides 128 GB/s of bidirectional bandwidth over x16 lanes. PCIe 6.0, already seeing adoption in SSDs since early 2025, doubles that figure to 256 GB/s and is expected to appear in upcoming Nvidia and AMD graphics cards. The jump to PCIe 8.0 would therefore represent another doubling, pushing performance far beyond present-day limits for data-intensive tasks.

According to the draft, final ratification of the complete PCIe 8.0 specification is scheduled for 2028. Widespread deployment in personal computers, game consoles, and smartphones is projected around 2031 or later, aligning with the typical multi-year cycle for new interconnect standards to reach consumer hardware. The specification continues to emphasize backward compatibility with earlier generations.

The PCI-SIG presented these details during a recent briefing that also highlighted ongoing evaluation of new connector technology to support the increased speeds. Electrical parameters remain subject to adjustment as the specification progresses toward full release. Frandroid reported the announcement based on coverage from Tom's Hardware.

Industry observers note that such bandwidth increases are driven by demands from AI workloads and high-performance computing, where higher throughput between processors, accelerators, and storage becomes essential. The draft maintains the use of PAM4 signaling and forward error correction introduced in prior generations while introducing protocol enhancements aimed at efficiency.